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By Zinn S.

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A test set dependent approach for power minimization is dependent on the size and the type of the test set employed during test application. A test set independent approach for power minimization depends only on the circuit structure and savings are guaranteed regardless of the size and the type of the test set. 3 25 Power Concerns During Test With the advent of deep sub-micron technology and tight yield and reliability constraints‚ in order to perform a non-destructive test for high performance VLSI circuits power dissipation during test application should not exceed the power constraint set by the power dissipated during functional operation of the circuit [18‚ 42‚ 69‚ 99‚ 149].

However, the computation time in [17, 33] is high due to the complexity of the test vector reordering problem which is reduced to finding a minimum cost Hamiltonian path in a complete, undirected, and weighted Approaches to Handle Test Power 35 36 POWER-CONSTRAINED TESTING OF VLSI CIRCUITS graph. The high computation time is overcome by the techniques proposed in [38, 45, 50], where test vector reordering assumes a high correlation between switching activity in the CUT and the Hamming distance [38, 50] or transition density [45] at circuits’ primary inputs.

Three orthogonal directions have been identified based on: test set dependence, the number of clock cycles required to apply a test vector and the location of test sources and sinks. Since test resource sharing determines resource allocation conflicts power-constrained test scheduling was also summarized. 1 Introduction To decrease the complexity of ATPG for sequential circuits structured DFT is required. The most commonly used DFT method employed for increasing the testability of VLSI digital circuits is the scan method [1].

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